[WayBack] Why Skylake CPUs Are Sometimes 50% Slower – How Intel Has Broken Existing Code – Alois Kraus reports that the PAUSE instruction on Intel Skylake architecture takes an order of magnitude longer than on previous architectures.
This impacts spinlock code in .NET 4.x and .NET Core 2, and likely impacts other spinlock code as well. The .NET core fix gets back-ported to .NET 4.x.
Since Delphi XE, the Delphi RTL code has borrowed ideas from .NET implementing this kind of code, so I filed [WayBack] QualityCentral: 144063 PAUSE instruction on Intel Skylake takes order of magnitude longer: important for SpinWait/SpinLock code (because Google can index it).
It is no coincidence that a Senior Scaleability Engineer at Booking.com mentioned it on his G+ stream ([WayBack] The “Pause” instruction changed timing dramatically in Skylake. Spinlock implementation based on pause will need adjustments. – Kristian Köhntopp – Google+) as changes like this can heavily impact server systems.
–jeroen
via: [WayBack] The “Pause” instruction changed timing dramatically in Skylake. Spinlock implementation based on pause will need adjustments.I hope a fix for this will be back-ported for many Delphi versions. – Jeroen Wiert Pluimers – Google+